1. Field of the Invention
The present invention relates to a computer raster graphics system which produces picture images by way of a raster manner.
2. Description of the Prior Art
Recently, with developed high performance microprocessor and inexpensive high-density memory element, a computer graphics technology has been developed. Particularly, animation and real-time simulation of a three-dimensional object is actively studying.
In general, such a high-performance system which assists a three-dimensional graphics includes a geometry engine functioning transformation process (that is, changing a position size to denote a graphic image in the computer graphics) and a clipping process (that is, removing an image portion out of a boundary of a display unit in the computer graphic) and a raster engine serving to rasterize.
The raster engine has a bottleneck which results from repeated operations and frequent access to a frame buffer for scan converting, black surface removement and shading (or rendering).
However, with an advanced high-performance engine (or processor) developed recently, an accessing time to the frame buffer is an important bottleneck factor in a graphic pipeline than the operation capability of the engine. For this reason, a method of processing multiple pixels simultaneously in parallel to achieve a high speed rasterization is considered.
Such a conventional system employs a cache memory to improve performance and operating speed of the system.
FIG. 1 shows a conventional raster graphics system. As seen in FIG. 1, the system has a pixel cache memory 20 between a scan converter 10 which generates data related to the respective pixels and a frame buffer memory 30 which stores pixel data.
The pixel cache 20 has a capacity smaller than that of the buffer but has an access time higher than that of the frame buffer 30 (substantially approx. 5-10 times higher). Interface between the frame buffer 30 and the pixel cache 20 results in that a plurality word (or block) unit of data is transferred to thereby increase the band width between the frame buffer 30 and the pixel cache 20 and, also, the working time of the system is reduced due to locality of reference.
Referring to FIG. 4, a general pixel map between frame buffers FB0 to FB3 is illustrated.
Substantially, the pixel cache is defined in a tile formation which is formed by a plurality of rectangular pixels or linearly arranged pixels. Accordingly, the number of pixels which are updated per cycle depends on the size of the tile.
Assuming that the larger the tile a large number of pixels per cycle are updated. Therefore, a high performance of the system can be assured but the cost of the pixel cache is relatively increased.
Further, the number of pixels to be updated per cycle depends on the structure of the tile and operation type thereof. That is, in a video image represented by way of a vector drawing and a wireframe (a formation of an object is three-dimensionally described by a large quantity of lines so as to represent a three-dimensional object formation in computer graphics), more pixels are updated (that is cache hit) in a rectangular tile structure (for example, 4.times.4). Alternatively, in polygon fill and shading or horizontal vector drawing, wire pixels are updated in a structure in which pixels are linearly arranged along an X-axis, that is, a matrix structure of 16.times.1.
This specification will be described with reference to a pixel cache of which a tile is formed by 8.times.8 pixels for easily understanding the present invention.
Now, the operation of such a conventional system will be described with reference FIG. 5.
FIG. 5(A) illustrates a pixel cache in which pixel data is stored by the scan converter (refer to 10 in FIG. 1).
The pixel data in the pixel cache is transferred to and stored in a predetermined area of the frame buffer, as shown in FIG. 5 (B) and the pixel cache is then cleared.
When the pixel data is stored in the block or tile of the frame buffer, the pixel data pre-stored in the frame buffer is stored in the pixel cache as shown in FIG. 5(C) so as to prevent the pre-stored data frame being damaged. This prevents the area in the frame buffer where existing pixel data is stored from being set and cleared to values of 0 when a tile of pixel cache written new vector pixel data is transferred and stored in the frame buffer.
When a cache failure occurs, the pixel data stored in the pixel cache is written into the frame buffer.
With such a conventional system, however, when the cache failure occurs, the pixel data stored in the frame buffer is stored in the pixel cache as new pixel data is supplied to the frame buffer.
As a result, one drawback is that the load in the data transfer between the pixel cache and the frame buffer undesirably increases.